TI公司的ADS5294是80MSPS/14位 8路ADC,具有低功耗,高SNR和低SFDR,以及連續(xù)過(guò)載恢復(fù),適用于高性能系統(tǒng)設(shè)計(jì). ADS5294具有數(shù)乁信號(hào)處理核,包括數(shù)字濾波器模塊, 可編程數(shù)字增益0 dB到12 dB,內(nèi)部和外接基準(zhǔn)電壓,1.8V工作電壓,主要用在超聲圖像,通信設(shè)備和多路數(shù)據(jù)采集.本文介紹了ADS5294主要特性,方框圖, 模擬輸入模型和電路,評(píng)估模塊測(cè)試圖以及評(píng)估模塊電路圖,材料清單和PCB布局圖.
Using CMOS process technology and innovative circuit techniques, the ADS5294 is a low power 80MSPS 8-Channel ADC. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high performance systems.
The ADS5294 has a digital processing block that integrates several commonly used digital functions for improving system performance. It includes a digital filter module that has built-in decimation filters (with low-pass, high-pass and band-pass characteristics).
The decimation rate is also programmable (by 2, by , or by 8). This makes it useful for narrow-band applications, where the filters can be used conveniently to improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) can be averaged to improve SNR.
Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC can be output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at high sample rate. The ADC resolution can be programmed to 12 bit or 14 bit through register. A very unique feature is the programmable mapping module that allows flexible mapping between the input channels and the LVDS output pins. This helps greatly reduce the complexity of LVDS output routing and can potentially result in cheaper system boards by reducing the number of PCB layers.
The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. The device can be driven with external references as well. The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292 QFP. It is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292.
ADS5294主要特性:
Maximum Sample Rate: 80 MSPS/14-Bit
High Signal-to-Noise Ratio
75.5-dBFS SNR at 5 MHz/80 MSPS
78.2-dBFS SNR at 5 MHz/80 MSPS and Decimation Filter Enabled
84-dBc SFDR at 5 MHz/80 MSPS
Low Power Consumption
58 mW/CH at 50 MSPS
77 mW/CH at 80 MSPS (2 LVDS Wire Per Channel)
Digital Processing Block
Programmable FIR Decimation Filter and Oversampling to
Minimize Harmonic Interference
Programmable IIR High Pass Filter to Minimize DC Offset
Programmable Digital Gain: 0 dB to 12 dB
2- or 4- Channel Averaging
Flexible Serialized LVDS Outputs:
One or Two Wires of LVDS Output Lines per Channel
Depending on ADC Sampling Rate
Programmable Mapping Between ADC Input Channels and
LVDS Output Pins-Eases Board Design
Variety of Test Patterns to Verify Data Capture
by FPGA/Receiver
Internal and External References
1.8V Operation for Low Power Consumption
Low-Frequency Noise Suppression
ADS5294應(yīng)用:
Ultrasound Imaging
Communication Applications
Multi-channel Data Acquisition
