ADI公司的AD9277是低成本低功耗小型容易使用的8路14位ADC,包括8路可變?cè)鲆娣糯笃?VGA)和低噪音放大器(LNA),抗混淆濾波器(AAF)和14位10MSPS到50MSPS本世紀(jì)末ADC以及可編相位旋轉(zhuǎn)的I/Q解調(diào)器,主要用在醫(yī)療圖像和超聲波圖像以及汽車(chē)?yán)走_(dá).本文介紹了AD9277主要特性和產(chǎn)品亮點(diǎn),方框圖, 超聲波系統(tǒng)方框圖以及AD9277評(píng)估板主要特性,評(píng)估板連接圖,電路圖,PCB布局圖和材料清單.此外還介紹了ADI醫(yī)療超聲解決方案方框圖和信號(hào)鏈接圖.
The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.
Each channel features a variable gain range of 42 dB, a fully differ-ential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.
The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.
Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9277 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of ?40°C to +85°C.
AD9277產(chǎn)品亮點(diǎn):
Small Footprint. Eight channels are contained in a small, space-saving package. Full TGC path, ADC, and I/Q demodulator contained within a 100-lead, 16 mm × 16 mm TQFP.
Low Power. In TGC mode, low power of 207 mW per channel at 50 MSPS. In CW mode, ultralow power of 94 mW per channel.
Integrated High Dynamic Range I/Q Demodulator with Phase Rotation.
Ease of Use. A data clock output (DCO±) operates up to 480 MHz and supports double data rate (DDR) operation.
User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements.
Integrated Second-Order Antialiasing Filter. This filter is placed before the ADC and is programmable from 8 MHz to 18 MHz.
AD9277主要特性:
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz typical at 5 MHz (gain = 21.3 dB)
SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB
Single-ended input: VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output: 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range: ?42 dB to 0 dB
Postamp gain: 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
14 bits at 10 MSPS to 50 MSPS
SNR: 73 dB
SFDR: 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel >160 dBFS/√Hz
Low power: 207 mW per channel at 14 bits/50 MSPS (TGC), 94 mW per channel for CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode: <2 μs
100-lead TQFP_EP
AD9277應(yīng)用:
Medical imaging/ultrasound
Automotive radar
