AP0100CS集成了Aptina的先進(jìn)圖像處理管道(pipeline)，具有令人驚嘆的視頻和低光照性能。借助用于寬動(dòng)態(tài)范圍圖像再現(xiàn)(rendering)的高級(jí)局部色調(diào)映射(Advanced Local Tone Mapping, ALTM)功能，即使在非常困難的高對(duì)比度照明條件下也能夠生成高質(zhì)量的視頻。AP0100CS集成了具有高級(jí)轉(zhuǎn)換器功能的NTSC/PAL編碼器，可以提供模擬CCTV市場(chǎng)所需的高TV線分辨率。
這款產(chǎn)品為中國市場(chǎng)設(shè)計(jì)人員提供了過去無法獲取全新相機(jī)設(shè)計(jì)方案;也就是說，能夠利用高端IP相機(jī)傳感器的高分辨率、內(nèi)在的卓越低光照性能及WDR能力，移植應(yīng)用于模擬CCTV監(jiān)控領(lǐng)域。這種強(qiáng)大的設(shè)計(jì)靈活性將會(huì)帶來令人激動(dòng)的新型監(jiān)控?cái)z像機(jī)。
典型操作
A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8- bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
單次隨機(jī)讀
Figure1 shows the typical READ cycle of the host to the address. The first two bytes sent by the host are an internal 16-bit register address. The following 2-byte READ cycle sends the contents of the registers to host.
Figure 1: Single READ from Random Location
